module delay_stage(
    input clk,
    input reset,
    input [63:0] i_pc,
    input [31:0] i_inst,
    input i_write_to_regfile,
    input [4:0] i_reg_addr,
    input [63:0] i_data_out,
    input i_inst_r_valid,
    input [63:0] i_mstatus,
    input [63:0] i_mtvec,
    input [63:0] i_mepc,
    input [63:0] i_mcause,
    input [63:0] i_mie,
    input [63:0] i_mip,
    input i_stall_from_mem,
    input i_mtime_int,

    output reg [63:0] o_pc,
    output reg [31:0] o_inst,
    output reg o_write_to_regfile,
    output reg [4:0] o_reg_addr,
    output reg [63:0] o_data_out,
    output reg o_inst_r_valid,
    output reg [63:0] o_mstatus,
    output reg [63:0] o_mtvec,
    output reg [63:0] o_mepc,
    output reg [63:0] o_mcause,
    output reg [63:0] o_mie,
    output reg [63:0] o_mip,
    output reg o_stall_from_mem,
    output reg o_mtime_int
);
    always @(posedge clk) begin
        if(reset) begin
            o_pc <= 64'h0000000080000000;
            o_inst <= 32'd0;
            o_write_to_regfile <= 1'b0;
            o_reg_addr <= 5'b00000;
            o_data_out <= 64'd0;
            o_inst_r_valid <= 1'b0;
            o_mstatus <= 64'd0;
            o_mtvec <= 64'd0;
            o_mepc <= 64'd0;
            o_mcause <= 64'd0;
            o_mie <= 64'd0;
            o_mip <= 64'd0;
            o_stall_from_mem <= 1'b0;
            o_mtime_int <= 1'b0;
        end else begin
            o_pc <= i_pc;
            o_inst <= i_inst;
            o_write_to_regfile <= i_write_to_regfile;
            o_reg_addr <= i_reg_addr;
            o_data_out <= i_data_out;
            o_inst_r_valid <= i_inst_r_valid;
            o_mstatus <= i_mstatus;
            o_mtvec <= i_mtvec;
            o_mepc <= i_mepc;
            o_mcause <= i_mcause;
            o_mie <= i_mie;
            o_mip <= i_mip;
            o_stall_from_mem <= i_stall_from_mem;
            o_mtime_int <= i_mtime_int;
        end
    end
    
endmodule